Electronic Warfare Algorithms Engineer

We are seeking an Electronic Warfare Algorithms Engineer to develop end-to-end processing pipelines—from raw IQ through detection, PDW extraction, pulse train formation, deinterleaving, and emitter identification. This role is algorithm-heavy and implementation-aware: you will design methods that can be realized on real-time platforms, collaborating closely with FPGA, CPU, and GPU specialists to translate theory into robust, testable capabilities. A strong command of Python, practical experience with SDRs, and the ability to validate behavior using lab instrumentation are central to success. Responsibilities: • Design and implement ESM signal processing chains covering: wideband capture, channelization, detection, PDW extraction, pulse train formation, deinterleaving, and emitter identification/classification. • Develop PDW extraction algorithms. • Build and tune detectors grounded in detection theory, especially CFAR variants. • Implement channelizers and multirate architectures: FFT channelizers, polyphase filter banks (PFB), multirate DSP. • Apply matched filtering and time-frequency processing to improve sensitivity (FFT processing gain, coherent/non-coherent integration, windowing effects). • Develop Direction Finding (DF) processing strategies appropriate to array/antenna geometries and operational constraints (including calibration-aware approaches). • Perform PRI / pulse pattern analysis, and design robust feature extraction for deinterleaving and identification. • Analyze and characterize agile/spread-spectrum signals (e.g., FHSS/DHSS) and define practical detection/feature extraction methods under realistic SNR and receiver constraints. • Determine performance limits using RF/system constraints: link budgets, Friis, receiver dynamic range, SFDR, ENOB, IIP3, phase noise, sampling/quantization effects, and front-end filtering limitations; translate these limits into actionable algorithm requirements. • Collaborate with FPGA/CPU/GPU engineers to map algorithms to hardware: throughput/latency budgeting, memory bandwidth considerations, fixed-point awareness, and verification strategies. • Build test harnesses and evaluation pipelines using real and synthetic datasets; produce clear documentation, plots, and quantitative results. Minimum Qualifications: • B.S. in Electrical Engineering. • 2+ years of professional industry experience (outside of academia) developing signal processing / EW / SDR / communications / radar-related algorithms. • Strong understanding of ESM/ELINT/COMINT/SIGINT domain concepts: what is measured, why it matters, and how systems operationalize extracted parameters. • Demonstrated competency in Python, especially NumPy/SciPy, for algorithm development, experimentation, and performance evaluation. • Solid grounding in detection theory and practical detector design, including CFAR and thresholding under non-ideal conditions. • Experience with channelizers, FFT-based processing, and multirate DSP concepts. • Experience working with SDRs as a user (capture/playback, gain setting, sampling strategy, calibration awareness), and comfort handling IQ datasets and metadata. • Ability to communicate effectively with cross-functional engineering teams and produce high-quality technical documentation. Preferred Qualifications: • M.S. in Electrical Engineering (or closely related) with focus in signal processing, RF, radar, or communications. • Knowledge of radar signal processing and array signal processing • Strong working knowledge of digital communications, including OFDM fundamentals. • Proficiency in C++ for performance-critical implementations or integration into production systems. • Familiarity with GNU Radio and common SDR stacks. • Experience with UHD and/or libiio (device configuration, streaming stability, rate/clocking considerations). • Practical experience with signal inspection/debug tooling (e.g., Inspectrum or equivalent workflows). • Hands-on comfort with RF lab equipment for validation and bring-up, including spectrum analyzers and signal generators (basic measurements, sanity checks, stimulus/response workflows). • Experience designing robust deinterleaving and identification pipelines under dense contested emitter environments. • Familiarity with real-time constraints and acceleration strategies (vectorization, SIMD, multiprocessing, GPU acceleration concepts) and collaboration with FPGA teams. Benefits: • Competitive salary and a comprehensive benefits package, including health insurance and fuel support. • Continued support for candidates currently enrolled in a master's or doctoral program. • Opportunities for continuous professional growth and skill development. • Engage in a collaborative and innovative work environment. • Enjoy a positive and enriching work environment, situated in a desirable location.