[Job Radar](https://jobradar.live/) / [Jobs](https://jobradar.live/ilanlar) / Principal Physical Design Engineer Active On-site Irvine, CA Posted · 22.09.2026 Greenhouse (US) # Principal Physical Design Engineer Celero Communications, Inc. Celero Communications is a fast-growing semiconductor startup developing high-performance coherent DSP technology for next-generation AI infrastructure. We recently announced a $275M Series C following the validation of the industry’s first 2nm coherent DSP silicon. Bloomberg also reported that Alphabet’s CapitalG has backed Celero at a $3B valuation. As we continue to grow, we’re hiring exceptional talent across the United States, Canada, and Argentina for a variety of exciting opportunities. We are seeking an experienced Physical Design Engineer to lead the transformation of complex circuit designs into high-quality, manufacturable silicon. In this role, you will drive all aspects of the physical implementation flow, including floorplanning, power planning, place-and-route (P&R), clock tree synthesis, timing closure, and physical verification. You will collaborate closely with architecture, RTL, circuit design, and verification teams to deliver high-performance chips that meet aggressive targets for performance, power, area (PPA), signal integrity, and manufacturability. As a technical leader, you will help define physical design methodologies, mentor engineers, and ensure successful tape-out of next-generation semiconductor products. Core Responsibilities • RTL-to-GDSII Execution: Own physical implementation of System-on-Chips (SoCs) or complex digital blocks. • Design Optimization: Manage floor-planning, bump planning, power grid design, and clock tree synthesis (CTS) to optimize chip performance. • Design Convergence: Resolve timing, congestions, EM/IR issues together with Frontend Designers • Signoff & Verification: Run Static Timing Analysis (STA) and physical verification. Fix Design Rule Checking (DRC) and Layout Versus Schematic (LVS) violations. • Methodology Development: Drive automation and improve flow robustness using scripting languages like Tcl, Python, or Perl. • Cross-Functional Leadership: Partner with architects, logic designers, and analog design team for tapeout readiness.  Key Qualifications • Must have 7+ years of relevant ASIC physical design experience (depending on degree level). • Process Knowledge: Deep tapeout experience in advanced technology nodes (e.g., 7nm, 5nm, 3nm). • Tool Mastery: Advanced proficiency with industry-standard EDA tools from vendors like Cadence (e.g., Innovus, Tempus, Voltus, Pegasus, Calibre). • Technical Concepts: Expertise in physically aware synthesis, power domain analysis, and Electromigration/IR-drop (EM/IR) cleanup. Annual Base Salary Range: $150,000 to $250,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location.) This job was verified from Greenhouse (US). Applications are completed on the original source. [Apply on the original listing ↗](https://jobradar.live/ilan/176768fb-5ff5-4a6d-a266-a2e8ec75d8ab/git) ## Stop searching one by one for roles like this. Upload your resume or enter your target roles to see your first 3 matches for free. [Find jobs for me →](https://jobradar.live/uye/kayit) Your resume is never shared with employers; it is processed only for matching. Something wrong with this job? ## Similar jobs [Celero Communications, Inc. Jobs](https://jobradar.live/company/celero-communications-inc) · [Jobs in California](https://jobradar.live/jobs/california) · [Jobs by location](https://jobradar.live/jobs) · [Jobs by company](https://jobradar.live/company) - [Growth Design Lead](https://jobradar.live/ilan/023cb9c3-14ed-42ac-ae78-2412cbbb07fe) Zapier · NAMER, California, United States - [Assembly Technician](https://jobradar.live/ilan/5ddbb0ea-612b-4de6-976d-ad43ed4e2fdf) Ready · FabLab - San Carlos, CA, California, United States - [Office Manager](https://jobradar.live/ilan/0178f2c2-585d-4b32-8fe4-4826e3e46dca) Ready · FabLab - San Carlos, CA, California, United States - [Senior Legal Engineer](https://jobradar.live/ilan/46403e2e-41ce-42b7-baa3-caa475c4ce63) Ontra · United States, CA - [Partner Experience Manager](https://jobradar.live/ilan/14ba4284-f3f0-4d21-8922-f1ea5c3792d1) Linq · San Francisco, California, United States - [Senior Electrical Engineer](https://jobradar.live/ilan/a1f62a41-9ee1-492c-a178-b00cad27ce2a) Kovari · San Francisco, California, United States - [Senior Mechanical Engineer](https://jobradar.live/ilan/4fd14b19-ec83-47ea-9a20-87c9c3c6d88a) Kovari · San Francisco, California, United States - [VP of Business Development](https://jobradar.live/ilan/89cee20d-da67-4c4e-a16d-69e573e58a69) Fourier · HQ, CA, USA