Electronic Warfare FPGA Engineer

We are seeking an Electronic Warfare FPGA Engineer to implement high-performance signal processing pipelines for SDR, EW/ESM systems. This role sits at the intersection of algorithm development and hardware realization: you will translate advanced DSP, radar, and EW concepts into deterministic, resource-efficient FPGA architectures while remaining hands-on in Python-based algorithm prototyping and validation. You will work closely with algorithm engineers, RF engineers, and embedded/FPGA teams to deliver real-time processing chains—from wideband IQ ingestion to detection, parameter extraction, and reporting—on modern FPGA platforms. Responsibilities DSP & EW Algorithm Implementation • Implement FPGA-based DSP pipelines for SDR, ESM, and EW systems. • Translate Python (NumPy/SciPy) and C++ algorithm prototypes into synthesizable HDL (VHDL/Verilog/SystemVerilog). • Optimize fixed-point representations and manage quantization trade-offs while preserving algorithmic performance. • Implement and optimize: CORDIC, CIC filters, Half-band filters, Polyphase filter banks (PFB), Perfect reconstruction filter banks, and Multirate DSP architectures. • Implement high-throughput FFT pipelines and leverage processing gain appropriately. Detection, Radar & ESM Processing • Implement detection pipelines grounded in signal detection theory, including in-depth CFARvariants and adaptive thresholding. • Implement radar and ESM-specific processing blocks such as pulse detection, parameter extraction, spectral analysis. • Contribute to or implement PDW extraction pipelines. • Translate radar and array signal processing concepts into FPGA-efficient architectures. Digital Communications Processing • Implement communications processing blocks including: Synchronization (symbol timing recovery, CFO estimation/compensation), Preamble detection and correlation, Pilot-based channel estimation • Understand SDR architectures and impairments and reflect those constraints in hardware design. Architecture & Hardware Awareness • Design memory-efficient architectures using: Block RAM (BRAM), UltraRAM (URAM), External DDR memory • Architect streaming pipelines with deterministic latency and controlled buffering. • Implement and optimize high-speed interfaces such as Ethernetand PCIe for data ingress/egress. • Work with RFSoC and direct RF sampling architectures where applicable. Algorithm Co-Development & Debug • Debug and improve DSP algorithms in Python as part of the development cycle. • Maintain high-quality algorithm validation workflows (golden reference models vs. HDL output comparison). • Use signal inspection tools (e.g., Inspectrum) to analyze captured IQ data and validate hardware behavior. • Perform bench-level validation using signal generatorsand spectrum analyzers. Verification & Integration • Develop simulation testbenches and verification infrastructure. • Use on-chip debug tools (ILA/VIO) for hardware debugging. • Collaborate with embedded and software engineers to integrate FPGA blocks into larger systems. • Participate in design reviews and contribute to performance/risk analysis. Minimum Qualifications • Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field. • 2+ years of professional FPGA development experience in DSP, radar, communications, or EW domains. • Strong foundational knowledge in: DSP theory, SDR architectures, Digital communications fundamentals, Radar signal processing, Signal detection theory • Deep understanding of CFAR and its practical implementation constraints in hardware. • Experience implementing polyphase filters, CIC filters, CORDIC, and FFT pipelines in FPGA. • Proficiency in Python (NumPy/SciPy) for algorithm development and debugging. • Ability to translate floating-point algorithm prototypes into efficient fixed-point HDL implementations. • Strong understanding of FPGA memory architectures (BRAM, URAM, DDR). • Experience with Ethernet and/or PCIe data movement architectures. • Hands-on experience with RF test equipment (spectrum analyzers, signal generators). Preferred Qualifications • Prior FPGA implementation of PDW extraction pipelines or ESM systems. • Familiarity with GNU Radio and SDR-based validation workflows. • Experience with high-throughput data streaming architectures and timing closure at scale. • Experience with hardware/software co-design and heterogeneous systems (CPU + FPGA). • Familiarity with CI/CD pipelines for FPGA builds and regression testing. • Experience with radar and array signal processing algorithms in FPGA. • Experience with RFSoC platforms and direct RF sampling systems. Benefits: • Competitive salary and a comprehensive benefits package, including health insurance and fuel support. • Continued support for candidates currently enrolled in a master's or doctoral program. • Opportunities for continuous professional growth and skill development. • Engage in a collaborative and innovative work environment. • Enjoy a positive and enriching work environment, situated in a desirable location.